The present invention generally relates to an apparatus for adjusting a phase of a frame signal in an external synchronization mode and for generating a frame reset pulse signal from the adjusted frame signal and a parallel clock (PCLK) of a video signal, and in particular, to an apparatus for preventing jitter when displaying a waveform of a SDI (Serial Digital Interface) video signal based on the frame reset pulse signal.
FIG. 1 represents a video signal waveform display apparatus 20 (a waveform monitor for instance) for inputting, from a video signal generator 12, a SDI video signal synchronized by a reference signal (EXT_REF, generally a black burst (BB) signal) from an external reference synchronizing signal generator 11, together with the reference signal (EXT_REF). As shown in FIG. 1, a SDI video signal waveform display apparatus 20 displays a waveform of SDI video signal from a SDI video signal generator 12 (a VTR or a camera for instance) in an external synchronization mode, that is, based on the external reference signal (EXT_REF). The SDI video signal waveform display apparatus 20 can input a SDI video signal from a SDI video signal generator 12A and a SDI video signal from a SDI video signal generator 12B and selects one of the SDI video signals so as to display the waveform of the selected SDI video signal based on the external reference signal (EXT_REF). It is possible, by using the same reference signal (EXT_REF) in the external synchronization mode, to grasp a phase difference between the SDI video signal (target signal) from the SDI video signal generator 12A and the SDI video signal (adjustment signal) from the SDI video signal generator 12B. Thereafter, it is possible, for the sake of eliminating the phase difference, to use a phase adjusting means (not shown) of the SDI video signal generator 12B for instance so as to adjust the phase of the SDI video signal outputted from the SDI video signal generator 12B. Thereby, it is possible to edit a plurality of SDI video signals.
Hereafter, operation of the SDI video signal waveform display apparatus 20 will be briefly described. First, a reference synchronizing signal generator 11 outside the waveform display apparatus 20 outputs a reference signal (EXT_REF signal, an analog signal) to the SDI video signal generator 12A. The SDI video signal generator 12A generates a SDI video signal (digital signal) synchronized based on the reference signal and outputs it to the SDI video signal waveform display apparatus 20, and also outputs the reference signal (analog signal) as it is to the SDI video signal generator 12B. The SDI video signal generator 12B generates a SDI video signal (digital signal) and outputs it to the SDI video signal waveform display apparatus 20 as with the SDI video signal generator 12A, and also outputs the reference signal (analog signal) as it is to the SDI video signal waveform display apparatus 20.
Next, the SDI video signal waveform display apparatus 20 can allow a user to select one of the inputted SDI video signals. The video signal selected by the user is inputted to a SDI video signal processing portion 21. The SDI video signal processing portion 21 inputs the SDI video signals from the SDI video signal generator 12 to generate a parallel clock (PCLK) from the SDI video signals. The SDI video signal processing portion 21 further generates parallel data based on the SDI video signals and the parallel clock (PCLK), and also outputs the parallel clock (PCLK) to an external reference synchronizing signal processing portion 22.
The external reference synchronizing signal processing portion 22 inputs the parallel clock (PCLK) from the SDI video signal processing portion 21 and the reference signal (analog signal: EXT_REF) outputted from the reference synchronizing signal generator 11 (SDI video signal generator 12B). FIG. 2 shows an example (prior art) of concretizing the external reference synchronizing signal processing portion 22 shown in FIG. 1. As shown in FIG. 2, the parallel clock (PCLK) from the SDI video signal processing portion 21 is inputted to a frame reset pulse generating circuit 22-2 of the external reference synchronizing signal processing portion 22. The reference signal (EXT_REF) from outside is inputted to a synchronizing separator circuit 22-1 of the external reference synchronizing signal processing portion 22. The synchronizing separator circuit 22-1 generates a frame signal (FRM) from the reference signal (EXT_REF), and outputs the frame signal (FRM) to the frame reset pulse generating circuit 22-2. The frame reset pulse generating circuit 22-2 generates a frame signal synchronized by the parallel clock from the parallel clock (PCLK) and the frame signal (FRM), and generates a frame reset pulse signal (FRM_RESET) based on the parallel clock (PCLK) and the frame signal synchronized by the parallel clock so as to output the frame reset pulse signal to the SDI video signal processing portion 21.
Returning to FIG. 1, the SDI video signal processing portion 21 uses the frame reset pulse signal as video output timing, and outputs the parallel data to a SDI video signal display processing portion 23 with the parallel clock (PCLK).
The SDI video signal display processing portion 23 processes the parallel data with the frame reset pulse signal and the parallel clock (PCLK) to generate waveform signal data for displaying a waveform of the SDI video signal. The SDI video signal display processing portion 23 outputs the waveform signal data to a display portion 24 (a display for instance) so that the SDI video signal is displayed as waveform on the display portion 24. The SDI video signal display processing portion 23 can also process the parallel data to create video signal data for displaying the video of the SDI video signal. In the case where a video display mode of the SDI video signal is selected by the user, the SDI video signal display processing portion 23 outputs the video signal data to the display portion 24 so that the SDI video signal is displayed as video on the display portion 24.